module MIPS(
    input wire clk,
    input wire rst,
    input wire [31:0]inst,
    input wire [31:0]rdData,
    output wire romCe,
    output wire [31:0]pc,
    output wire [31:0]wtData,
    output wire [31:0]memAddr,
    output wire memCe,
    output wire memWr
);



wire [31:0] regaData_i;
wire [31:0] regbData_i;
wire [5:0] op;
wire [31:0] regaData;
wire [31:0] regbData;
wire [31:0] jAddr;
wire jCe;
wire regcWr;
wire [4:0] regcAddr;
wire regaRd;
wire [4:0] regaAddr;
wire regbRd;
wire [4:0] regbAddr;

IF if0(
.clk(clk),
.rst(rst),
.jaddr(jAddr),
.jce(jCe),
.pc(pc),
.romCe(romCe)
);

wire hiRd;
wire loRd;

ID id0(
.rst(rst),
.pc(pc),
.inst(inst),
.regaData_i(regaData_i),
.regbData_i(regbData_i),
.op(op),
.regaRd(regaRd),
.regaAddr(regaAddr),
.regaData(regaData),
.regbRd(regbRd),
.regbAddr(regbAddr),
.regbData(regbData),
.regcWr(regcWr),
.regcAddr(regcAddr),
.jAddr(jAddr),
.jCe(jCe),
.hiRd(hiRd),
.loRd(loRd)
);

wire [31:0] regcData_ex;
wire [4:0] regcAddr_ex;
wire regcWr_ex;
wire [31:0] memAddr_ex;
wire [31:0] memData_ex;
wire [5:0] op_ex;
wire [31:0] hi;
wire [31:0] lo;
EX ex0(
.op_i(op),
.regaData(regaData),
.regbData(regbData),
.regcWrite_i(regcWr),
.regcAddr_i(regcAddr),
.rst(rst),
.regcData(regcData_ex),
.hi(hi),
.lo(lo),
.regcWrite(regcWr_ex),
.regcAddr(regcAddr_ex),
.op(op_ex),
.memAddr(memAddr_ex),
.memData(memData_ex)
);

wire [4:0] regAddr;
wire [31:0] regData;
wire regWr;
wire loWr;
wire hiWr;
wire [31:0] loData;
wire [31:0] hiData;

MEM mem0(
.rst(rst),
.op(op_ex),
.regcData(regcData_ex),
.regcAddr(regcAddr_ex),
.regcWr(regcWr_ex),
.memAddr_i(memAddr_ex),
.memData(memData_ex),
.rdData(rdData),
.hi(hi),
.lo(lo),
.regAddr(regAddr),
.regWr(regWr),
.loWr(loWr),
.hiWr(hiWr),
.loData(loData),
.hiData(hiData),
.regData(regData),
.memAddr(memAddr),
.wtData(wtData),
.memWr(memWr),
.memCe(memCe)
);

REGFILE regfile0(
.clk(clk),
.rst(rst),
.regaAddr(regaAddr),
.regbAddr(regbAddr),
.regaRd(regaRd),
.regbRd(regbRd),
.we(regWr),
.wAddr(regAddr),
.wData(regData),
.hiRd(hiRd),
.loRd(loRd),
.hiWr(hiWr),
.loWr(loWr),
.hiData(hiData),
.loData(loData),
.regaData(regaData_i),
.regbData(regbData_i)
);

endmodule



